Partners

Ramon Chips Ltd

(Israel)

RC

www.ramon-chips.com

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Ramon Chips is a fabless semiconductor company focused on developing unique VLSI / ASIC solutions for space applications. Its silicon proven RadSafe™ technology, comprising rad-hard-by-design (RHBD) libraries of digital cells, IO, memories, clocking etc. and a full-chip methodology for space rad-hard design at the logic and physical levels, provides extremely high immunity to all space radiation effects, while maintaining high density, high performance and low power. The company has expertise in designing digital and analogue radiation-hardened chips from specifications, synthesis of functions and algorithms into robust radiation-tolerant cores, and converting FPGA designs into radiation-hardened ASICs. The company has designed, fabricated, packed, qualified and rad-tested several successful rad-hard ASICs including GR712RC, a dual-core LEON3 SoC for space (in collaboration with Aeroflex Gaisler), JPIC, a JPEG2000 image compression ASIC and a controller for SAR payload.

Role in the project:

RC will apply its know-how towards developing the architecture of a high-performance rad-hard digital signal processor ASIC, will design and fabricate a prototype chip, and will design an emulation of the architecture in FPGA to enable developing benchmark programs, measuring performance and estimating performance of the target ASIC. RC will lead work packages 4 (Prototype Chips) and work packages 7 and 8 (project governance and technical coordination) but it will support the work in all the other work packages.

Digitale Signalverabeitungsysteme & Informationstechnik GmbH

(Germany)

DSI

http://www.dsi-it.de/

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DSI is a SME company, founded in 1997 focused on aerospace technology.   The fields of activity are dedicated to the engineering and development of solutions for computers, information technologies, control systems and advanced communication systems in aerospace applications, such as payload data handling systems, cryptographic systems, satellite communications and ground test equipment. DSI employs more than 40 engineers with the firm’s   headquarters located within the science park at the Bremen Airport in   Germany.

Role in the project:

DSI will implement the ManyCore DSP approach in a prototype system including the core chip (first stage FPGA, second stage prototype) plus an emulation of a typical environment (source data emulation, access to a typical space mass memory and sink data emulation). The research scope is how such a novel processor architecture approach with its features can be integrated into the classical payload data processing within various types of applications (communication, image processing etc.).

DSI will participate in most work packages of the project, and   will be the leader of work package 4. Being a supplier of payload and communication processors for space, DSI will provide to the project its set of special applications requirements and use cases, such as secure communications and onboard data evaluation and data compression.

CEVA Limited

(Ireland)

CEVA

http://www.ceva-dsp.com

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CEVA is the world’s leading licensor of DSP cores and   platform solutions for the mobile, digital home and networking markets. For more than twenty years, CEVA has been licensing a portfolio of DSPs, platforms and   software to leading semiconductor vendors and original equipment manufacturer (OEM) companies worldwide.  CEVA’s IP portfolio includes comprehensive technologies for cellular baseband (2G / 3G / 4G), image enhancement & vision, advanced audio and voice , Voice over IP (VoIP), Bluetooth, Serial Attached SCSI (SAS) and Serial ATA (SATA).

CEVA Limited forms part of the DSP VLSI Division of CEVA Inc. It   employs seven qualified engineers and, along with the CEVA R&D offices in other countries, is focused on the digital design of CEVA DSP Intellectual Property (DSP IP).

CEVA will be supported in the MacSpace project by CEVA DSP, the Israeli-based design centre.

Role in the project:

CEVA’s role in the project will be to develop the DSP IP Core   which will be used in the DSP computer. As such, CEVA will be WP leader of   WP3 (“DSP IP CORE”) and participate in and provide DSP technical support in the other work packages as appropriate. CEVA will perform an architectural study to review the project objectives against its existing mature and widely licensed DSP IP Cores portfolio to choose an appropriate DSP Core to form the baseline DSP Core design for this project. This architectural study shall specify what changes will be required to the baseline design for optimal performance in terms of (a) DSP Core hardware, (b) bus interfaces and memory sub-system hardware, (c) software compiler/development tools and (d) simulation and verification environment. The output from the architectural  study shall drive the subsequent optimised DSP IP implementation phase, comprising hardware, software and verification tasks. The output from the implementation phase shall be a full DSP Core IP package, including software  compiler/development tools which shall then be used in the subsequent work packages of the project. CEVA will also provide technical guidance and  support on the MacSpace DSP Core IP to other partners when implementing the   FPGA prototype and ASIC design.

TECHNISCHE UNIVERSITAET BRAUNSCHWEIG

(Germany)

TUBS

www.tu-braunschweig.de/c3e

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TUBS  is the oldest institute of technology in Germany: the cornerstone of this modern university was already laid in the year 1745 with the Collegium Carolinum. The computer science department at the TU Braunschweig has a long tradition. As one of the first universities in Germany, TUBS set up computer science courses as early as in 1972.

Its classic main areas are theoretical, practical, technical and applied computer science. In addition, the study of computer science at the TU Braunschweig offers a wide range of modern applications-oriented sub-areas of computer science, which extends from the computer graphics on embedded systems and computer science to medicine to robotics and ubiquitous computing (ubiquitous information technology).

Role in the project:

TUBS   will support the work of all the work packages. It will specifically be   involved in the full-system simulation for early benchmarking and evaluation,  development of benchmark applications and test scenarios, consulting with regard to parallel processing, parallel programming, and scalability.

THALES ALENIA SPACE ITALIA SPA

(Italy)

TAS-I

www.thalesaleniaspace.com

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TAS-I   is the Italian entity of Thales Alenia Space (TAS), with plants in Milano,   Torino, Roma and L’ Aquila. TAS-I is a joint venture between Thales 67 %)   and Finmeccanica (33 %). The company has 7,500 employees in France, Italy,   Spain, Belgium, Germany and United States, and posted total revenues of EUR 2.1 billion in 2011. European leader for satellite systems and at the forefront of orbital infrastructures, TAS-I is a worldwide reference in   telecom, radar and optical Earth observation, defence and security, navigation and science.

Featuring cutting-edge technologies, TAS-I systems meet the needs of commercial, government, scientific, defence and security customers from around the world. The satellites and payloads designed by TAS-I set the global standard for space systems that provide communications and navigation services, monitor our environment and the oceans, help us better understand climate change and drive scientific progress. TAS-I is also a leading supplier to the International Space Station, and a pivotal player in space systems designed to explore the Universe.

Role in the project:

Within the MacSpace project, TAS-I will play the role of the User/Operator.

First of all, the technical requirements for the device will be defined, starting from the needs expressed by the various entities belonging to the company, with reference to a wide set of reference applications. This will also result in requirements for the board implementation and testing provision.

The most significant applications will be then deepened to be implemented as ‘use cases’, both on initial FPGA and subsequently on final silicon, either by partners or by TAS-I itself. TAS-I will lead work package 1 (Requirements, use case and architecture) and work package 5 (Validation and testing).

PRESTO ENGINEERING EUROPE SA

(France)

PRESTO

www.presto-eng.com

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Presto Engineering provides comprehensive semiconductor product engineering and production solutions to IDM, fabless and electronics companies, contributing to improving ramp time, margins and quality of new products.

They are recognized experts in the development of test solutions, for component characterization and production. This expertise, combined with state of the art ESD, reliability and failure analysis capabilities, helps customers optimise end-product performance and accelerate time to market. They offer turn-key solutions from customer tape-out to delivery of finished goods to end-customer(s), including assembly, test, qualification, industrialization,   and production sustaining activities.

The company recently expanded in Europe by acquiring lab infrastructure from NXP Semiconductor in Caen, France, and ITH infrastructure in Israel, and opened a shared R&D Lab with CEA LETI in Grenoble (FR).

Role in the project:

PRESTO will develop the test environment and test engineering setup including hardware and software to validate the functionality and correlate with expected   behaviour and performances.

ARTTIC SAS

(France)

ARTTIC

www.arttic.eu

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twitter.com/ARTTIC_RTD

 

 

 

Created in 1987, ARTTIC SAS (ARTTIC) is a European provider of management services for international collaborative R&D projects. The ARTTIC group comprises several companies with offices in France, Belgium, Germany, the UK and Israel. ARTTIC’s total staff adds up to over 50 people, all specialised in the provision of advice and practical assistance in the set up and management of international R&D collaborative project.

Role in the project:

In the MacSpace project, ARTTIC will be work-package leader for the WP6 Dissemination and Exploitation, and a partner in WP7 Project Governance and Administration and WP8 Technical Coordination. ARTTIC will also be in charge of the day-to-day project management under supervision of the Coordinator. ARTTIC will provide methods, tools and operational support for the collaboration within the consortium and will support the consortium in the daily management and administrative tasks. It’s role is to ensure the collaboration is working efficiently, the project is properly monitored and decisions and actions are prepared and taken according to the project progress.

The MacSpace Consortium at the project kick-off meeting, January 2014, Israel. 

Team photo Jan 2014 v4