Project Objective

The project’s objective is to research, develop and validate a “High-Performance ManyCore Rad-Hard DSP for Computation-Intensive Space Applications”.

The key measurable outcomes expected at the end of the project are:

  1. The MacSpace DSP Computer architecture, and associated DSP Core IP, which will enable the MDC to achieve the target performance and performance-to-power levels presented in Table 1.
  2. A prototype MacSpace Processor chip, with performance indicative of the target performance levels.
  3. Emulated MacSpace DSP Computer (MDC) achieving the target performance levels:
    • When the project ends, around mid-2016, the MacSpace Processor will have reached a computational performance of 75 GMACS / 150 GOPS / 20 GFLOPS;
    • Performance of emulated MacSpace DSP Computer extrapolated to required performance of (high performance computational) benchmarks;
    • Performance of emulated full MDC system extrapolated to set balanced performance of system/application benchmarks (e.g., Telecom PLD, etc.).

        Table 1 – Target MacSpace Processor Functions and Performance

MacSpace Processor: 64    FXD/FP cores, 4 Mbytes*

MacSpace Processor Functions


Performance    / Power



Functionality as identified by Joint   EC-ESA-EDA task force [EU-2012]

Floating point; Radiation hardness; High-speed interfaces; Interfaces to ADC, DAC


Rad-hard implementation for total dose hardness, no SEL and high SEU immunity

300 kRad

High speed interfaces

DDR2/3 interface

25 Gbps

High-speed serial interfaces

120 Gbps aggregated

Parallel LVDS interface to ADC/DAC

38 Gbps


10 W

Clock Freq.

300 MHz


(floating point)


3.8 GFLOPS/Watt



75 GMACs

7.5   GMACs/Watt


(fixed point)

150 GOPS

15 GOPS/Watt

ESA benchmark B2

(FFT 4096)

2 Gsps^

200 Msps/Watt

ESA benchmark B5

(demodulator and filter)

500 Msps^

50 Msps/Watt

*Each core is a DSP core with performance of 1×32 bit or 4×16 bit or 4 x 8bit MACs per cycle. Namely, in each cycle it can perform either one multiplication and accumulation of two 32 bit arguments, or four multiplications and four accumulations of 16 bit arguments, or four multiplications and four accumulations of 8bit arguments i.e. a total of 8 fixed point operations. 64 cores executing at 300 MHz achieve peak rate of 64×0.3×4=76.8 GMACS for 16bit or 8bit arguments.

^Preliminary estimation